This invention relates to a semiconductor memory device in which memory cells can be accessed by an address supplied to an address bus and an address obtained by adding "1" to the supplied address.
Generally, a row of memory cells in a memory cell array of a semiconductor memory device is selected by a row address signal, with one cell from among the selected row being selected by a column address signal. In other words, a given memory cell is selected by row and column address signals and is then accessed.
In a computer system employing such a semiconductor memory device as described above, a specific memory system may be used. In such a memory system, the same address is assigned to a preset number of memory bits (n-bits) as one unit, and a unit of processing amount (which is called a word) handled by a CPU may be constituted by 2.sup.m .times.n bits. In this case, the memory system is constituted by 2.sup.m memory banks which are each constituted by an n-bit memory. Each of the 2.sup.m memory banks is supplied with common row and column address signals, thereby permitting data to be read out from corresponding memory cells of the respective memory banks.
With this construction, a word starting at an address of an integer multiple of 2.sup.m can be accessed during each operation of accessing the memory system. However, this being the case, it is then impossible to access to a word starting at a desired address. In order to be able to access a word starting at a desired address, it then becomes necessary to use a plurality of address incrementers, for incrementing by one the address supplied to the memory bank, and an address selector for selecting output data from the address incrementer or normal address (an address not incremented). However, use of such address incrementers increases the length of time necessary to access the desired memory cell, since additional time is required for the address incrementer to increment the address by one.